Nanometer-scale InGaAs Field-Effect Transistors for THz and CMOS technologies

Integrated circuits based on InGaAs Field Effect Transistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and space communication systems. InGaAs ICs are also under intense research for new millimeter-wave applications such as collision avoidance radar and gigabit WLANs. InGaAs FET scaling has nearly reached the end of the road and further progress to propel this technology to the THz regime will require significant device innovations. Separately, as Si CMOS faces mounting difficulties to maintain its historical density scaling path, InGaAs-channel MOSFETs have recently emerged as a credible alternative for mainstream logic technology capable of scaling to the 10 nm node and below. To get to this point, fundamental technical problems had to be solved though there are still many challenges to be addressed before the first non-Si CMOS technology becomes a reality. The intense research that this exciting prospect is generating is also reinvigorating the prospects of InGaAs FETs to become the first true THz electronics technology. This paper reviews progress and challenges of InGaAs-based FET technology for THz and CMOS.Focus Center Research Program. Center for Materials, Structures and DevicesIntel CorporationUnited States. Army Research LaboratorySemiconductor Research Corporatio

The High-Electron Mobility Transistor at 30: Impressive Accomplishments and Exciting Prospects

2010 marked the 30th anniversary of the High-Electron Mobility Transistor (HEMT). The HEMT represented a triumph for the, at the time, relatively new concept of bandgap engineering and nascent molecular beam epitaxy technology. The HEMT showcased the outstanding electron transport characteristics of two-dimensional electron gas (2DEG) systems in III-V compound semiconductors. In the last 30 years, HEMTs have been demonstrated in several material systems, most notably AlGaAs/GaAs and AlGaN/GaN. Their uniqueness in terms of noise, power and high frequency operation has propelled HEMTs to gain insertion in a variety of systems where they provide critical performance value. 2DEG systems have also been a boon in solid-state physics where new and often bizarre phenomena have been discovered. As we look forward, HEMTs are uniquely positioned to expand the reach of electronics in communications, signal processing, electrical power management and imaging. Some of the most exciting prospects in the near future for HEMT-like devices are those of GaN for high voltage power management and III-V CMOS to give a new lease on life to Moore’s Law. This paper briefly reviews some highlights of HEMT development in the last 30 years in engineering and science. It also speculates about potential future applications

Time evolution of electrical degradation under high-voltage stress in GaN high electron mobility transistors

In this work, we investigate the time evolution of electrical degradation of GaN high electron mobility transistors under high voltage stress in the OFF state. We found that the gate current starts to degrade first, followed by degradation in current collapse and eventually permanent degradation in I[subscript D]. We also found that the time evolution of gate current degradation is unaffected by temperature, while drain current degradation is thermally accelerated

Injection velocity in thin-channel InAs HEMTs

We have experimentally extracted the virtual-source electron injection velocity in InAs HEMTs with a 5 nm thick channel. For long gate lengths, these devices exhibit noticeably worse injection velocity than thicker channel devices of a similar design. However, for very short gate lengths, as the devices approach the ballistic regime, the extracted injection velocity becomes rather independent of channel thickness. From these results, we can conclude that InAs-based QW-FETs with very thin channels have the potential of scaling to very short dimensions.Intel CorporationSemiconductor Research Corporation. Center for Materials, Structures and Device

The prospects for 10 nm III-V CMOS

The increasing difficulties for further scaling down of Si CMOS is bringing to the fore the investigation of alternative channel materials. Among these, III-V compound semiconductors are very attractive due to their outstanding electron transport properties. This paper briefly reviews the prospects and the challenges for a III-V CMOS technology with gate lengths in the 10 nm range.Semiconductor Research CorporationIntel Corporatio

InGaAs/InAs heterojunction vertical nanowire tunnel FETs fabricated by a top-down approach

We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at V[subscript ds]= 0.3 V is obtained over 2 decades of current. On the same device, I[subscript on]= 0.27 μA/μm is extracted at V[subscript dd]= 0.3 V with a fixed I[subscript off]= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials.National Science Foundation (U.S.). Center for Energy Efficient Electronics Science (Award 0939514

Lifetime estimation of intrinsic silicon nitride MIM capacitors in a gan MMIC process

CS MANTECH Conference, May 18th-21st, 2009, Tampa, Florida, USAWe have studied the reliability of intrinsic SiN MIM capacitors designed for 48 V and 125 [superscript 0]C operation and manufactured in a GaN process flow. It is shown that very small area capacitors (10um x 10um) with a dielectric thickness of 400nm exhibit lifetimes as long as 1.48E10 hours under such conditions

Analysis and Optimization of Multi-Winding Toroidal Inductors for Use in Multilayered Technologies

The aim of this paper is to compare the performance of planar toroidal inductors and circular spiral inductors in multilayered technologies, in terms of achievable inductance density. New multi-winding toroidal inductor geometry is proposed to cover as much of the integration area as possible with the component footprint. The optimization of planar multi-winding toroidal inductors in multilayered substrates is investigated theoretically, and closed formulae are derived for their inductances as a function of geometrical parameters for any given value of the number of windings in the coil. The model obtained is validated experimentally and through electromagnetic simulation. Comparing the inductance of multi-winding toroidal inductors and compact spiral inductors allows us to update previously reported selection rules for the most suitable topology that leads to the most compact design

High-Frequency InAIAs/InGaAs Metal-Insulator-Doped Semiconductor Field-Effect Transistors (MIDFETs) for Telecommunications

Contains an introduction and reports on experiments and device results.Joint Services Electronics Program Contract DAAL03-89-C-0001Charles S. Draper Laboratory Contract DL-H-40418

III-V CMOS: What have we learned from HEMTs?

The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic performance has recently come into question. An end to Moore's Law threatens to bring to a halt the microelectronics revolution: a historical 50 year run of exponential progress in the power of electronics that has profoundly transformed human society. The outstanding transport properties of certain III-V compound semiconductors make these materials attractive to address this problem. This paper outlines the case for III-V CMOS, harvests lessons from recent research on III-V High Electron Mobility Transistors (HEMTs) and summarizes some of the key challenges in front of a future III-V logic technology